Interpreting the RAMCHECK
Test Log for DDR Devices

INN-8668-APN15
--Updated 5-13-2005

1. The test log will be automatically displayed after the Basic test ends unless you press the "ESC" key to terminate the test.
2. You can press "F5" anytime during the Basic Test to view the test log.
3. The test log can be viewed anytime after you start the Basic test by simply pressing the "ESC" key after the Basic test is completed. Once in standby mode press "F4" then "F1" for "View Test Log", use "F4" to go forward through the screens and "F3" to go back. Once finished simply press the "ESC" key to go back to standby mode.
4. By installing the RAMCHECK PC Communications program that was included with your RAMCHECK on your PC and connecting your RAMCHECK to your computer via the serial cable you can view, save or print out the complete test log for future reference.

RAMCHECK Display	Description
	BASIC TEST The test phase use by the RAMCHECK. DDR DUT DETECTED - UBF Describes the type of DUT (Device Under Test) that you are testing, in this case DDR. "Type" is unbuffered display as "UBF", please see below. CONNECTOR WIRING - OK At the start of the Basic Test the RAMCHECK performs a wiring test to verify that the Control lines are properly wired and functional. In this instance it reported no errors.
	STRUCTURE TEST -> Starts a brief test to determine the structure of the DDR module. All information that follows is the structure of the DDR device as detected by the RAMCHECK.
	BANK BITS DETECTED: BANK 1: CB DQ63-32 DQ31-0 00 FFFFFFFF FFFFFFFF BANK 2: CB DQ63-32 DQ31-0 00 00000000 00000000 This is a new feature added to RAMCHECK firmware version 2.21 and higher for DDR devices, which gives you a brief description of the structure of the DDR device by mapping the DQ and CB (Parity) bits by the module's individual banks. This feature is very useful in troubleshooting DDR Modules with severe or multiple errors.
	DATA WIRING - PASS ADD. WIRING - PASS At the start of the Basic Test the RAMCHECK performs a wiring test to verify that the Data and Address lines are properly wired and functional. In this case it reported no errors. TEST AT SSTL 2.5V The DDR module is being tested at 2.5 volts. SIZE: 32Mx64=256M Shows the size of the DDR module in both JEDEC notation and overall size.
	CHIP SIZE: 4x8Mx8 Shows the size of the individual DDR chips of the DDR module in JEDEC notation. 13 ROW/10 COL ADDR. Shows the number of rows and columns detected by the RAMCHECK. REFRESH:AUTO Shows that the refresh rate is in Auto mode which will use the RAMCHECK's default value of 50ms.
	BANKS: 1 -S:0 DQS:08..0 DM: 08..0 Shows a brief description of the structure of the DDR module similar to the "BANKS BITS DETECTED" shown above, but by displaying the number of banks and individual control lines that were detected by the RAMCHECK. SPD=JEDEC Conforms to JEDEC standards. DDR 184P DIMM Shows the form factor of the DDR module, in this case a 184-pin DIMM.
	TEST TABLE #22 CODE=1067 The "TEST TABLE" and "CODE" indications are used as part of our factory development to identify certain characteristics of the DDR device. These identifications can also be used as a form of comparison to other DDR devices. TYPE: UNBUFFERED The RAMCHECK detected the DDR module as conforming to the JEDEC standard for Unbuffered configurations. Other types may include Registered, etc. ECC=N The RAMCHECK detected that this DDR module does not have (ECC) Error Correction Code wiring. If "ECC=Y" was displayed then ECC would have been detected.
	CLOCKS:3 CK0+1+2 The RAMCHECK detected the use three clock inputs and displayed which clock inputs it detected. BL TEST=2, 4, 8 - OK The RAMCHECK tested the operation of the 3 burst lengths available in DDR devices, -2,4 and 8. In this instance it indicates that BL (Burst Length) tested ok on all three. SPD=CL2.5 - 333MHz SPD=CL2 - 266MHz SPD=PC2700 Any time you see "SPD=" in the test log, it always refers to the information read directly from the SPD chip on the DDR device which is programmed by the module's manufacturer. In this case the SPD claims that this module is a PC2700 with the CAS Latencies set accordingly. You can also view the "SPEED TEST RESULT" describe below to see if the SPD information compares with the RAMCHECK's test results.
	ARRAY TEST @ CL2 -> Ends the "STRUCTURE TEST" and starts the "ARRAY TEST @ CL2" where the entire memory array is written and verified twice at CL=2 to catch most cell stuck problems. ARRAY TEST - OK No errors were detected at CL2. ARRAY TEST @ CL2.5 -> Starts the "ARRAY TEST @ CL2.5" where the entire memory array is written and verified twice at CL=2.5 to catch most cell stuck problems.
	ARRAY TEST - OK No errors were detected at CL2.5 SPEED TEST RESULT: TEST= PC2700 FINAL SPEED:333MHz The RAMCHECK determined that this DDR module is within PC2700 specifications with its ending Basic Test speed as being 333MHZ.
	BASIC TEST OK TIME: 00:13.9 Shows the DDR device passed the Basic Test along with the test time in seconds.

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